Most, if not all, modern Phase Locked Loop (PLL) systems having low loop bandwidths require some circuit means of ensuring fast lock-up on application of an applied signal to prevent excessive acquisition times. In addition to reducing lock up time these fast lock circuit means normally enable the PLL to acquire lock even when the error frequency is many times greater than the loop bandwidth. The most common technique used to decrease lock up time is to increase loop gain when the system is out of lock. Increasing the loop gain increases the loop bandwidth and hence decreases lock up time. This technique suffers in that loop gain can only be increased to the point where loop instability becomes a problem.
In an attempt to overcome the above described problem a PLL system was developed utilizing a pair of phase detectors for generating quadrature phase related beat notes from the applied input signal. The beat notes are used in combination with a RS latch circuit to generate a square wave at the output of the RS latch circuit. This square wave is out of phase with the beat note generated from the reference one of the pair of detectors when the frequency of the input signal is greater than the Voltage Controlled Oscillator (VCO) frequency and is in phase when the input signal frequency is below the VCO frequency. In this manner the appropriate half of the reference phase detector output current is increased in such a way that the PLL is driven towards lock. A PLL of this type is used in the MC13020 AM Stereo Decoder Integrated Circuit manufactured by Motorola, Inc. The MCl3020 PLL is described in more detail with reference to FIG. 1 herein. Although the MC13020 PLL performs quite well it also suffers from system problems. For instance, the lock up time is still limited by loop stability considerations. Further, the circuit paths between the two phase detectors and the RS latch circuit are dissimilar and therefore have different signal delays therebetween. This sets a limit to the maximum error in frequency between the input signal and the VCO signal that the PLL can handle since at higher frequency beat notes the input signals to the RS latch circuit are no longer in phase quadrature.
Thus, there is a need for an improved PLL system having fast lockup circuitry which overcomes the problems associated with prior art PLL .